In an array substrate of a thin film transistor liquid crystal display (TFT-LCD), for the active layer in the TFT, an IGZO (indium gallium zinc oxide) material having a high mobility is widely used, and meanwhile, a splicing screen is also increasingly and widely used in our daily lives. The gate insulating layer material of the IGZO active layer is generally made of SiOx or SiOx/SiNx composite material, and an etching rate of SiOx is lower and an etching time is longer in comparison with SiNx. As shown in FIG. 1, which is a structural diagram of an array substrate having one drilling process in the prior art. In FIG. 1, a structural diagram of a partial structure of a thin film transistor (TFT) using a back channel etching (BCE) structure is shown. The structure mainly includes a first metal layer 11′, a gate insulating layer 12′, a second metal layer 13′ (forming an active layer, a source and a drain made of IGZO), a passivation layer 14′ and an indium tin oxide (ITO) layer 15′, which are sequentially deposited on the glass substrate 10′. It can be shown that the connection between the ITO layer 15′ and the second metal layer 13′, the first metal layer 11′ is achieved by performing the drilling process after depositing the passivation layer to form a deep hole and a shallow hole. However, such a process may have disadvantages, because in order to cooperate with the deep hole etching, the shallow hole etching time is too long, and the via hole coking residue may occur, thus resulting in excessive via hole contact resistance and poor conduction performance, which may cause display abnormality. This situation generally occurs to in-plane small holes.
For solving the problem of residual in-plane via hole residue, in some processes, a step of trenching the gate insulating layer is added. Namely, the gate insulating layer and the passivation layer are respectively drilled, so that there is no foregoing deep hole and shallow hole situation. As shown in FIG. 2, which is a structural diagram of an array substrate having two drilling processes in the prior art, although this method can solve the problem of the in-plane via hole residue, in the splicing screen shown in FIG. 3, the upper half screen (AA-1) and the lower half screen (AA-2) are respectively connected to the bonding area 17′, the upper half screen and the lower half screen will have a charge mismatch in the process, and in case that the out-of-plane regions of the upper and lower half screens both adopt gate insulating drilling process, it is easy to accumulate static electricity during the drying process. Therefore, in a screen splicing middle position of the common electrode layer 16′ (COM), and there is a voltage difference of charges of the upper and lower half screens to form an electrostatic discharge (ESD), which causes the display panel to fail to display normally, and even a film is peeled off due to ESD, the subsequent process cannot be implemented.